The need for increasing performance is driving the use of smaller and local memory macros that are embedded in the various circuit functions of custom integrated circuits. However there is a large amount of support circuitry associated with each memory macro in order to test the memory macros. The support circuits consume significant silicon area thus increasing the cost of the integrated circuits. Therefore, there is a need to reduce the area impact of test circuits of embedded memory macros without significant reduction in test coverage or increase in test time.